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| March 2004 (R) AS7C1026B 5 V 64K X 16 CMOS SRAM Features * Industrial and commercial versions * Organization: 65,536 words x 16 bits * Center power and ground pins for low noise * High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time * Low power consumption: ACTIVE - 605 mW / max @ 10 ns * TTL-compatible, three-state I/O * JEDEC standard packaging * ESD protection 2000 volts * Latch-up current 200 mA - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 Pin arrangement 44-Pin SOJ (400 mil), TSOP 2 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC * Low power consumption: STANDBY - 55 mW / max CMOS I/O * 6 T 0.18 u CMOS technology * Easy memory expansion with CE, OE inputs Logic block diagram A0 Row decoder A1 A2 A3 A4 A5 A6 A7 I/O0-I/O7 I/O8-I/O15 VCC I/O buffer Control circuit Column decoder A8 A9 A10 A12 A13 A14 A15 A11 WE UB OE LB CE Selection guide -10 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current -12 12 6 100 10 -15 15 7 90 10 AS7C1026B 64 K x 16 Array GND -20 20 8 80 10 Unit ns ns mA mA 10 5 110 10 3/26/04, v 1.3 Alliance Semiconductor P. 1 of 10 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C1026B (R) Functional description The AS7C1026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words x 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The device is packaged in common industry standard packages. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Symbol Vt1 Vt2 PD Tstg Tbias IOUT Min -0.50 -0.50 - -65 -55 - Max +7.0 VCC +0.50 1.0 +150 +125 20 Unit V V W C C mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE H L L L L L L L L WE X H H H L L L H X OE X L L L X X X H X LB X L H L L L H X H UB X H L L L H L X H I/O0-I/O7 High Z DOUT High Z DOUT DIN DIN High Z High Z I/O8-I/O15 High Z High Z DOUT DOUT DIN High Z DIN High Z Mode Standby (ISB), ISBI) Read I/O0-I/O7 (ICC) Read I/O8-I/O15 (ICC) Read I/O0-I/O15 (ICC) Write I/O0-I/O15 (ICC) Write I/O0-I/O7 (ICC) Write I/O8-I/O15 (ICC) Output disable (ICC) Key: H = high, L = low, X = don't care. 3/26/04, v 1.3 Alliance Semiconductor P. 2 of 10 AS7C1026B (R) Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature commercial industrial Symbol VCC VIH VIL TA TA Min 4.5 2.2 -0.5 0 -40 Nominal 5.0 - - - - Max 5.5 VCC + 0.5 0.8 70 85 Unit V V V o o C C VIL min = -1.0V for pulse width less than 5ns VIH max = VCC+2.0V for pulse width less than 5ns. DC operating characteristics (over the operating range)1 -10 Parameter Input leakage current Output leakage current Operating power supply current -12 -15 -20 Sym | ILI | | ILO | ICC Test conditions VCC = Max, VIN = GND to VCC VCC = Max, CE = VIH, VOUT = GND to VCC VCC = Max, CE VIL, IOUT = 0mA, f = fMax CE VIH , f = fMax VCC = Max, CE VCC-0.2 V, VIN 0.2 V or VIN VCC-0.2 V, f = 0 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min VCC = Max, Min Max Min Max Min Max Min Max Unit - - 1 1 - - 1 1 - - 1 1 1 1 A A - 110 - 100 - 90 - 80 mA ISB Standby power supply current ISB1 VOL VOH - 50 - 45 - 45 40 mA - - 2.4 10 0.4 - - - 2.4 10 0.4 - - - 2.4 10 0.4 - 2.4 10 0.4 - mA V V Output voltage Capacitance (f = 1MHz, Ta = 25 C, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE, LB, UB I/O Test conditions VIN = 0 V VIN = VOUT = 0 V Max 5 7 Unit pF pF 3/26/04, v 1.3 Alliance Semiconductor P. 3 of 10 AS7C1026B (R) Read cycle (over the operating range)3,9 -10 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE low to output in low Z CE high to output in high Z OE low to output in low Z Byte select access time Byte select Low to low Z Byte select High to high Z OE high to output in high Z Power up time Power down time Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tBA tBLZ tBHZ tOHZ tPU tPD Min 10 - - - 3 3 - 0 - 0 - - 0 - Max - 10 10 5 - - 4 - 5 - 5 4 - 10 -12 Min 12 - - - 3 3 - 0 - 0 - - 0 - - 12 12 6 - - 5 - 6 - 6 5 - 12 15 - - - 3 3 - 0 - 0 - - 0 - -15 Max - 15 15 7 - - 6 - 7 - 6 6 - 15 20 3 3 0 0 0 -20 Min Max Unit 20 20 8 7 8 7 7 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 4, 5 4, 5 5 4, 5 4, 5 4, 5 3 3 Notes Max Min Key to switching waveforms Rising input Falling input Undefined output/don't care Read waveform 1 (address controlled)3,6,7,9 tRC Address DataOUT tOH Previous data valid tAA Data valid tOH 3/26/04, v 1.3 Alliance Semiconductor P. 4 of 10 AS7C1026B (R) Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9 tRC Address tAA OE tOLZ CE tLZ LB, UB tBLZ DataIN tBA Data valid tBHZ tACE tOHZ tHZ tOE tOH Write cycle (over the operating range) 11 -10 Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Byte select low to end of write tWC tCW tAW tAS tWP tWR tAH tDW tDH tWZ tOW tBW 10 8 8 0 7 0 0 5 0 - 1 7 - - - - - - - - - 5 - - 12 9 9 0 8 0 0 6 0 - 1 8 -12 - - - - - - - - - 6 - - 15 10 10 0 9 0 0 8 0 - 1 9 -15 - - - - - - - - - 7 - - 20 12 12 0 12 0 0 10 0 2 9 -20 Unit ns ns ns ns ns ns ns ns ns ns ns ns 5 4, 5 4, 5 Notes 8 Symbol Min Max Min Max Min Max Min Max 3/26/04, v 1.3 Alliance Semiconductor P. 5 of 10 AS7C1026B (R) Write waveform 1 (WE controlled)11 tWC tAH Address tCW CE tBW LB, UB tAS WE tDW DataIN tWZ DataOUT Data undefined Data valid tOW high Z tDH tAW tWP tWR Write waveform 2 (CE controlled)11 tWC Address tAS CE tCW tAW tBW LB, UB tWP WE tDW DataIN tCLZ DataOUT high Z tWZ Data undefined high Z Data valid tOW tDH tWR tAH 3/26/04, v 1.3 Alliance Semiconductor P. 6 of 10 AS7C1026B (R) AC test conditions - - - - Output load: see Figure B. Input pulse level: GND to 3.5 V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5 +5 V 480 +3.5V GND DOUT 90% 10% 2 ns 90% 10% 255 C13 Thevenin Equivalent: 168 DOUT +1.728 V Figure A: Input pulse GND Figure B: 5 V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 3/26/04, v 1.3 Alliance Semiconductor P. 7 of 10 AS7C1026B (R) Package dimensions 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 c 44-pin TSOP 2 Min (mm) Max (mm) 1.2 0.05 0.95 0.30 44-pin TSOP 2 E He A A1 A2 0.15 1.05 0.45 0.21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 b c D D l 0-5 A1 b e 0.120 18.31 10.06 18.52 10.26 11.94 0.60 A A2 E He e l 11.68 0.40 0.80 (typical) D e 44-pin SOJ 400 mil Min (in) Max (in) A A1 A2 0.128 0.025 0.105 0.026 0.015 0.007 1.120 0.395 0.435 0.148 - 0.115 0.032 0.020 0.013 1.130 0.405 0.445 44-pin SOJ E1 E2 Pin 1 B A2 A A1 b c B b c D E E1 E2 e Seating plane E 0.370 NOM 0.050 NOM 3/26/04, v 1.3 Alliance Semiconductor P. 8 of 10 AS7C1026B (R) Ordering codes Package \ Access time Plastic SOJ, 400 mil TSOP 2, 10.2 x 18.4 mm Temp commercial industrial commercial industrial 10 ns AS7C1026B-10JC AS7C1026B-10JI AS7C1026B-10TC AS7C1026B-10TI 12 ns AS7C1026B-12JC AS7C1026B-12JI AS7C1026B-12TC AS7C1026B-12TI 15 ns AS7C1026B-15JC AS7C1026B-15JI AS7C1026B-15TC AS7C1026B-15TI 20 ns AS7C1026B-20JC AS7C1026B-20JI AS7C1026B-20TC AS7C1026B-20TI Note: Add suffix `N' to the above ordering part number for LEAD FREE PARTS (Ex: AS7C1026B-10JCN) Part numbering system AS7C SRAM prefix 1026B Device number -XX Access time X Package: X X N = LEAD FREE PART Temperature range: C = commercial: 0 C to 70 C J = SOJ 400 mil T = TSOP 2, 10.2 x 18.4 mm I = industrial: -40 C to 85 C 3/26/04, v 1.3 Alliance Semiconductor P. 9 of 10 AS7C1026B (R) (R) Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: AS7C1026B Document Version: v 1.3 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. |
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